| Processor Core |
PowerPC ISA-compliant 32-bit single issue RISC processor (RCPU) |
| FPU |
64-bit Floating Point Unit |
| Memory Controller |
Unified system integration unit (USIU) with a flexible memory controller and enhanced interrupt
controller (EIC) |
| Data Bus Width |
32-bit |
| Addressable Memory |
4 GB |
| Level 1 Cache |
??? |
| Internal Memory |
32-Kbytes of static RAM in one CALRAM module, configured as
28-Kbyte normal access only array
4-Kbyte normal access or overlay access array (eight 512-byte regions)
2 KB of DECRAM providing additional
RAM used for compression tables
IRAMSTBY regulator permits retention
of SRAM data in low power mode |
| Flash EEPROM |
512-Kbytes of Flash EEPROM memory
Typical endurance of 100,000 write/erase cycles @ 25ºC
Typical data retention of 100 years @ 25ºC |
| Time Processing Units |
Two time processing units (TPU3) with one 8-Kbyte dual port TPU RAM (DPTRAM) |
| Modular I/O |
One 22-timer channel modular I/O system (MIOS14) |
| Controller Area Network |
Three TouCAN modules |
| Queued ADC |
Two enhanced queued analog systems (QADC64E)
10-bit,
unipolar, successive approximation converters |
| QSMCM |
One queued serial multi-channel module (QSMCM), which contains one queued serial peripheral
interface (QSPI) and two serial controller interfaces (SCI/UART) |
| Debug features |
Nexus debug port (Class 3)
Background debug mode (BDM)
IEEE 1194.1-compliant interface (JTAG) for boundary scan |
| Independent power supplies |
5-V I/O (5.0 ± 0.25 V)
2.6 ± 0.1-V external bus with a 5-V tolerant I/O system
2.6 ± 0.1-V internal logic
<150μA on-chip voltage shunt regulator for RAM standby operation |
| Code Compression |
Supports code compression, saving both memory and ROM space |
| Other Features |
One peripheral pin multiplexing module (PPM) with a parallel to serial driver |
