| Processor Core |
Power Architecture MPC603e processor core |
| FPU |
64-bit floating-point unit |
| Data Bus Width |
32-bit |
| Addressable Memory |
2 GB Physical |
| Level 1 Cache |
16-Kbyte, four-way set-associative Instruction Cache
16-Kbyte, four-way set-associative Data Cache |
| On-Chip Peripherals |
32-bit PCI interface operating at up to 66 MHz
General Purpose I/O and ROM Interface Support
Two-channel DMA controller that supports chaining
Messaging unit with I2O messaging support capability
Industry-standard I2C interface
Programmable interrupt controller with multiple timers and counters
16550 compatible Dual-UART (DUART) |
| Memory Interface |
133 MHz memory bus capability
Programmable timing EDO DRAM or SDRAM
High-bandwidth bus (32/64-bit data bus) to DRAM
Supports one to eight banks of 16-, 64-, 128, 256 or 512Mbit DRAM
Supports 1 Mbyte to 2 Gbyte DRAM memory
Contiguous memory mapping
272 Mbytes of ROM space
8-bit, 16-bit, 32-bit, or 64-bit ROM
Supports bus-width writes to flash
Read-modify-write parity support (selectable)
ECC support (selectable)
SDRAM, DRAM buffer data-path
Error injection/capture on data path
LVTTL compatible
PortX: 8-, 16-, 32- or 64-bit general-purpose I/O port uses ROM controller interface with address strobe |
| 32-bit PCI interface |
PCI 2.2 compatible
PCI 5.0 V tolerant
Support for PCI locked accesses to memory
Support for accesses to all PCI address spaces
Selectable big- or little-endian operation
Store gathering of processor-to-PCI writes and PCI-to-memory writes
Memory prefetching of PCI read accesses
Parity support (selectable)
Selectable hardware-enforced coherency
PCI bus arbitration unit (5 request/grant pairs) |
| PCI agent mode capability |
Address Translation Unit (ATU)
Run time register access
PCI configuration register access |
| Integrated DMA controller |
Dual-channel
Supports direct or chaining modes
Scatter gather
Interrupt on completed segment, chain, and error
Local to local memory
PCI to PCI memory
PCI to local memory
Local to PCI memory |
| Message Unit |
(I2O) Intelligent Input/Output Message Controller
Two door-bell registers
Inbound and outbound messaging registers |
| (I2C) Inter-Integrated Circuit Controller |
Full master/slave support |
| Embedded PIC (EPIC) |
Five hardware interrupts (IRQs) or 16 serial interupts
Four programmable timers |
| Debug Features |
Watchpoint monitor
Memory attribute and PCI attribute signals
JTAG/COP - Common On-board Processor for in-circuit hardware debugging |
| Other Features |
Integrated PCI bus and SDRAM clock generation
Programmable memory and PCI bus drivers |
