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Freescale MPC8250 PowerQUICC II Processors

Processor Core	Embedded Power Architecture G2 Core
FPU	Fully IEEE 754-compliant FPU for both single- and double-precision operations
Data Bus Width	64-bit (on 60x Bus, using 32-bit addressing) 32-bit (on Local Bus, using 18-bit addressing) 32-bit (on 60x to PCI Bridge)
Addressable Memory	4 GB
Level 1 Cache	16-Kbyte, four-way set-associative Instruction Cache 16-Kbyte, four-way set-associative Data Cache
64-bit data and 32-bit address 60x bus	Bus supports multiple master designs Supports single- and four-beat burst transfers 64-, 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller Supports data parity or ECC and address parity
32-bit data and 18-bit address local bus	Single-master bus, supports external slaves Eight-beat burst transfers 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller
60x-to-PCI bridge	Programmable host bridge and agent 32-bit data bus, 66 MHz, 3.3 V Synchronous and asynchronous 60x and PCI clock modes All internal address space available to external PCI host DMA for memory block transfers PCI-to-60x address remapping
System interface unit (SIU)	Clock synthesizer Reset controller Real-time clock (RTC) register Periodic interrupt timer Hardware bus monitor and software watchdog timer IEEE 1149.1 JTAG test access port
Twelve-bank memory controller	Glueless interface to SRAM, page mode SDRAM, DRAM, EPROM, Flash and other userdefinable peripherals Byte write enables and selectable parity generation 32-bit address decodes with programmable bank size Three user programmable machines, general-purpose chip-select machine, and page-mode pipeline SDRAM machine Byte selects for 64 bus width (60x) and byte selects for 32 bus width (local) Dedicated interface logic for SDRAM
Communications processor module (CPM)	Embedded 32-bit communications processor (CP) uses a RISC architecture for flexible support for communications protocols Interfaces to G2 core through on-chip 32-Kbyte dual-port RAM and DMA controller Serial DMA channels for receive and transmit on all serial channels Parallel I/O registers with open-drain and interrupt capability Virtual DMA functionality executing memory-to-memory and memory-to-I/O transfers Three fast communications controllers supporting the following protocols: 10/100-Mbit Ethernet/IEEE 802.3 CDMA/CS interface through media independent interface (MII) Transparent HDLC—Up to T3 rates (clear channel) One multichannel controller (MCC2) Handles 128 serial, full-duplex, 64-Kbps data channels. The MCC can be split into four subgroups of 32 channels each. Almost any combination of subgroups can be multiplexed to single or multiple TDM interfaces up to four TDM interfaces per MCC Four serial communications controllers (SCCs) identical to those on the MPC860, supporting the digital portions of the following protocols: Ethernet/IEEE 802.3 CDMA/CS HDLC/SDLC and HDLC bus Universal asynchronous receiver transmitter (UART) Synchronous UART Binary synchronous (BISYNC) communications Transparent Two serial management controllers (SMCs), identical to those of the MPC860 Provide management for BRI devices as general circuit interface (GCI) controllers in time division- multiplexed (TDM) channels Transparent UART (low-speed operation) One serial peripheral interface identical to the MPC860 SPI One inter-integrated circuit (I2C) controller (identical to the MPC860 I2C controller) Microwire compatible Multiple-master, single-master, and slave modes Up to four TDM interfaces Supports one group of four TDM channels 2,048 bytes of SI RAM Bit or byte resolution Independent transmit and receive routing, frame synchronization Supports T1, CEPT, T1/E1, T3/E3, pulse code modulation highway, ISDN basic rate, ISDN primary rate, Freescale interchip digital link (IDL), general circuit interface (GCI), and user-defined TDM serial interfaces Eight independent baud rate generators and 20 input clock pins for supplying clocks to FCCs, SCCs, SMCs, and serial channels Four independent 16-bit timers that can be interconnected as two 32-bit timers
PCI bridge	PCI Specification Revision 2.2 compliant and supports frequencies up to 66 MHz On-chip arbitration Support for PCI to 60x memory and 60x memory to PCI streaming PCI Host Bridge or Peripheral capabilities Includes 4 DMA channels for the following transfers: PCI-to-60x to 60x-to-PCI 60x-to-PCI to PCI-to-60x PCI-to-60x to PCI-to-60x 60x-to-PCI to 60x-to-PCI Includes all of the configuration registers (which are automatically loaded from the EPROM and used to configure the MPC8265A) required by the PCI standard as well as message and doorbell registers Supports the I2O standard Hot-Swap friendly (supports the Hot Swap Specification as defined by PICMG 2.1 R1.0 August 3, 1998) Support for 66 MHz, 3.3 V specification 60x-PCI bus core logic which uses a buffer pool to allocate buffers for each port Makes use of the local bus signals, so there is no need for additional pins
Other features	CPU core can be disabled and the device can be used in slave mode to an external core