| Type |
2-bit Bipolar Bit-Slice Central Processing Element |
| Cycle Time |
100ns cycle time
By my calculation, this gives a clock speed of 10MHz. However, other sources give the clock speed as 6 MHz... |
| Compatibility |
TTL and DTL Compatible |
| Bus Organisation |
N-Bit Word Expandable Multi-Bus Organization:
3 Input Data Busses
2 Three-State Fully Buffered Output Data Busses |
| Registers |
11 General-Purpose Registers |
| Addressable Memory |
Uses an independant Memory Address Register, which is part of the 3001 MCU. This allows up to 512 microinstruction addresses to be addressed (organised as 32 rows x 16 columns) |
| Instruction Set |
8 Function Groups
Over 40 Useful Functions
Zero
Detect and Bit test |
| Data Bus Width |
2-2N bits |
| Other Features |
Full Function Accumulator
Cascade Outputs for Full Carry Look-Ahead |
| |
|
| When N/2 3002's are connected together, forming a CPU with a word length of N-bits, the following capabilities are present: |
| |
- 2's complement arithmetic
- Logical AND, OR, NOT and XOR
- Increment and Decrement
- Shift left or right
- Bit testing and zero detection
- Carry look-ahead generation
- Multiple data and address busses
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